1. Field of the Invention
This invention relates to semiconductor memories, particularly to non-volatile memories using variable threshold transistors.
2. Description of the Prior Art
Non-volatile variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors store information by holding charge in the gate dielectric of the transistor. The presence or absence of charge in the gate dielectric of the transistor results in a change in the threshold voltage of the transistor. For example, in MNOS memory arrays, an electrical bias across the gate and body of a selected transistor will cause electron tunneling through a thin oxide layer to the nitride oxide interface. The charge stored on the nitride oxide interface decays with time and with the number of read-write cycles the device has endured. In addition, the non-uniformity of variable threshold transistor device characteristics from transistor to transistor as a result of processing an array of memory transistors make information retrieval by detection of the absolute threshold voltage of a variable threshold transistor a problem.
One memory array arrangement to enhance information retrieval has been to use two variable threshold transistors per memory cell where one device is written as the complement of the other. A wide spread in the threshold voltage, V.sub.T, of the two transistors in the memory cell enable detection of the memory cell by comparison of the two threshold voltages. The two variable threshold transistors of the memory cell will have experienced the same processing and read-write history which may not effect the difference in threshold voltages between the two transistors. This technique, however, requires two transistors per memory cell.
It is therefore desirable to provide the detection of a memory cell comprising a single memory transistor by comparing its threshold voltage with the threshold voltage of another memory transistor comprising a memory cell having a known or detected memory state.
It is therefore desirable to provide a means to detect the memory state of a memory cell utilizing one transistor by detecting changes in the threshold voltage between adjacent memory transistors in a memory array.
It is therefore desirable to provide a technique for detecting the memory state of a memory cell utilizing one transistor by sequentially comparing the threshold voltage of a memory transistor with an adjacent memory transistor. Although there may be significant and undetermined differences and characteristics from memory transistor to transistor across a memory array, adjacent memory transistor differences will be small when adjacent memory transistors are in the same memory or logic state and will be large when they are in opposite or complement memory or logic states.